1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2011-119360, filed May 27, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, the nanoscaling of semiconductor devices such as DRAMs (dynamic random-access memories) is progressing. As a result, if the gate length of a transistor becomes short, there is caused the short-channel effect in the transistor becoming prominent, the sub-threshold current increasing, and the transistor threshold voltage (Vt) decreasing.
Increase in impurity concentration of the semiconductor substrate to suppress the decrease of the transistor threshold voltage (Vt) will increase the junction leakage current.
For this reason, nanoscaling DRAM memory cells in a DRAM as a semiconductor device will deteriorate refresh characteristics.
Japanese Patent Application Publications Nos. JPA 2006-339476 and JPA 2007-081095 disclose a so-called trench gate transistor (recessed-channel transistor), in which a gate electrode is buried in a trench formed in the front surface side of the semiconductor substrate.
By making the transistors trench gate transistors, it is possible to physically and sufficiently achieve an effective channel length (gate length), thereby enabling a DRAM having nanoscaled cells with a minimum process dimension of 60 nm or smaller.
In Japanese Patent Application Publication No. JPA 2007-081095, there is disclosed a DRAM having two trenches formed to be adjacent to one another in a semiconductor substrate, a gate electrode formed in each of the trenches with an intervening gate insulating film therebetween, a first impurity diffusion region common to the two gate electrodes formed on the surface of the semiconductor substrate and positioned between the two gate electrodes, and a second impurity diffusion region formed on the surface of the semiconductor substrate and positioned on the element separation region side of the two gate electrodes.